1. Field of the Invention
The present invention relates to a semiconductor memory that operates in synchronization with a clock signal.
2. Description of the Related Art
As a semiconductor memory that operates in synchronization with a clock signal, a synchronous DRAM is known, for example. This type of semiconductor memory transmits an input signal (e.g., address signal) received by an input circuit to a latch circuit during a period in which a chip enable signal is active, and latches the transmitted signal in synchronization with a clock signal. The latched signal is supplied to a decoder and the like.
A system for accessing the semiconductor memory supplies the input signal and the chip enable signal to the semiconductor memory in synchronization with the clock signal. For example, Japanese Unexamined Patent Application Publication No. 10-55665 describes that, in order to surely latch the address signal in synchronization with the clock signal, an operation margin of an internal circuit of the semiconductor memory is used to make the period in which the chip enable signal is active longer than a valid period of the input signal.
On the other hand, a pseudo SRAM, a pseudo DRAM or the like, is known as a semiconductor memory that is not synchronized with a clock signal. This type of semiconductor memory controls an input circuit for receiving an input signal such as an address signal, by a chip enable signal in order to reduce a stand-by current. In other words, the stand-by current is reduced by activating the input circuit only during a period in which the chip enable signal is active. The input signal received by the input circuit is latched by a signal obtained by delaying the chip enable signal, and is then supplied to a decoder and the like.